PERFORMANCE ENHANCEMENT OF 8 BIT RISC ARCHITECTURE

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Published Feb 25, 2021
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Pratik Katwate
Electronics & Telecommunication Department Rajarambapu Institute of Technology Islampur, India
Sanjay Pardeshi
Electronics & Telecommunication Department Rajarambapu Institute of Technology Islampur, India
Vardhman Tiwatane
Head. R&D Vsoft Technology, Pimple Nilakh Pune,India

Abstract

In this paper we have selected PIC16A84 processor as base platform for the enhancement of its features. Selected processor is based on the 8bit RISC platform. The intention is to enhance the capabilities of the soft-core in terms of 16 bit arithmetic operations. Addition of new blocks tested by adding the new instruction in the instruction set.

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How to Cite
Pratik Katwate, Sanjay Pardeshi, & Vardhman Tiwatane. (2021). PERFORMANCE ENHANCEMENT OF 8 BIT RISC ARCHITECTURE. JournalNX - A Multidisciplinary Peer Reviewed Journal, 209–212. Retrieved from https://repo.journalnx.com/index.php/nx/article/view/2340