DESIGN AND IMPLEMENTATION OF 8-BIT VEDIC MULTIPLIER

Authors

  • MISS. RUTUJA ABHANGRAO Student, Electronics & Telecommunication Department, SKNSCOE Sinhgad college of engineering Korti Pandharpur Solapur India.
  • MISS. SHILPA JADHAV Student, Electronics & Telecommunication Department, SKNSCOE Sinhgad college of engineering Korti Pandharpur Solapur India
  • MISS PRIYANKA GHODKE Student, Electronics & Telecommunication Department, SKNSCOE Sinhgad college of engineering Korti Pandharpur Solapur India
  • PROF. ALTAAF MULANI H. O. D., Electronics & Telecommunication Department, SKNSCOE Sinhgad College of engineering Korti Pandharpur Solapur India,

Keywords:

Vedic Multiplier, Urdhva Tiryagbhyam, Digital Signal Processing

Abstract

Today's technology has raised demand for fast and real time signal processing operation. Multiplication is one of the most important arithmetic operations. In this paper, we have proposed design of vedic multiplier using Urdhva Tiryagbhyam sutra in Xilinx ISE. This design takes lesser time for operation than currently available multipliers .It encompasses wide era of image processing and digital signal processing in much efficient way with increase in speed and thus leading to higher performance rating

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Published

2021-03-03

Issue

2017: NCMTEE

Section

Articles

License

Creative Commons License

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

How to Cite

DESIGN AND IMPLEMENTATION OF 8-BIT VEDIC MULTIPLIER. (2021). JournalNX - A Multidisciplinary Peer Reviewed Journal, 24-26. https://repo.journalnx.com/index.php/nx/article/view/2610